1. Field of the Invention
The present invention relates to a memory access control device and a control method thereof, and more particularly, to a memory access arbitrating device capable of selectively generating a second writing request after a delay time for ensuring the correctness of the memory access requests of a single-port memory when a first writing request and a first reading request are overlapped, and a controlling method thereof.
2. Description of the Prior Art
Recent technological progress and the requirements for modern computing system have resulted in higher requirements for speeds of data reading, transmission, storing and displaying, and accuracy of the aforementioned operations, wherein a critical point of the performance of a computing system is the memory access operations corresponding to the computing system.
It is therefore an important issue to ensure access efficiency of memory devices, to optimize the performance of the whole system accordingly. However, the progress of technology and the requirements for a variety of functions have led to computing systems of ever increasing complexity. A memory access request control device must arrange the order of incoming access commands appropriately, especially when the memory access control device receives different types of memory access requests (e.g. a memory reading request and memory writing request) at the same time, for avoiding the memory access requests being omitted/reduplicated erroneously and for ensuring the stability and correctness of the single port memory.
A conventional memory access control device includes a memory read request generating module, a memory write request generating module, a pulse width control module corresponding to the memory read request generating module, a pulse width control module corresponding to the memory write request generating module, and an arbitrator.
The memory read request generating module and the memory write request generating module of the conventional memory access control device are implemented for generating read requests and write requests, respectively, according to the received memory access events when a computing system outputs a memory read command/memory write command (a read/write event) to a single-port memory. That is, the computing system has to control the access operations to the single-port memory by generating a memory access command (access event) Event_WR/Event_RD via controlling the conventional memory access control device to output a memory read grant signal/memory write grant signal (Grant_RD/Grant_WR).
When the computing system outputs the memory write command/event Event_WR to the single-port memory, the write request generating module simultaneously generates a corresponding memory write request Req_WR to the arbitrator according to the memory write event Event_WR; when the computing system generates a memory read command/event Event_RD to the single-port memory, the read request generating module generates a memory read request Req_RD to the arbitrator that corresponds to the memory read event Event_RD. The arbitrator then arbitrates a priority between the memory read/write commands for generating the corresponding memory access grant signals according to the received memory read request/memory write request Req_RD/Req_WR. For example, the arbitrator generates the memory read grant signal/memory write grant signal Grant_RD/Grant_WR to the single-port memory, thereby allowing the computing system to execute the memory read operations/memory write operations according to the memory read grant signal/the memory write grant signal Grant_RD/Grant_WR.
That is, the required time for the single-port memory to execute a memory read operation and the required time to execute a memory write operation are respectively restricted by the pulse width control module corresponding to the memory read operation and the pulse width control module corresponding to the memory write operation, wherein the amount of time taken for the memory read operation and the memory write operation are determined by the specification with which the single-port memory complies.
Please refer to FIG. 1. FIG. 1 is a diagram illustrating signals of a conventional memory access control device. Please note that each of the memory access events (Event_RD/Event_WR) is synchronized with the corresponding memory access request (Req_RD/Req_WR).
That is, a corresponding write request is generated simultaneously when a write event occurs. FIG. 1 illustrates an example of a collision between a memory read event and a memory write event. In this example, the arbitrator sets a memory read grant signal Grant_RD as logic “1” when a memory read request Req_RD is logic “1” since, at this time, there is no collision between memory access operations of the single-port memory. In other words, the single-port memory performs the corresponding memory read operation while the memory read grant signal Grant_RD is logic ‘1’.
However, when the memory write request Req_WR is converted from logic “0’ to logic “1” the arbitrator sets the corresponding memory write grant signal Grant_WR from logic “0” to logic “1” for permitting the single-port memory to execute the memory write operation only after the memory read grant signal Grant_RD is converted from logic “1” to logic “0” (i.e., the memory read operation corresponding to the memory read grant signal is finished) due to a single-port memory being restricted to executing one access operation at a time.
This restriction leads to a following memory write request Req_WR not being permitted to be set as logic “1” before the pulse width control unit corresponding to the memory write control module finishes a memory write grant process corresponding to a former memory write operation. The following memory write request Req_WR is allowed only after the memory write grant signal Grant_WR is converted from logic “1’ to logic “0”.
An allowed write period (P_WR) between two write grant signals therefore cannot be smaller than a summation value of a time magnitude (T_RD) of one read grant signal and a time magnitude (T_WR) of one write grant signal Grant_WR. The aforementioned restriction is expressed by the equation:P—WR≧T—WR+T—RD. 
The performance of memory write operations is excessively affected by the memory write period P_WR. There is therefore a demand to design a system and a control method thereof for reducing the time magnitude of the memory write period P_WR, to promote the performance of the memory write operations.